搜索结果: 1-9 共查到“军事学 coprocessor”相关记录9条 . 查询时间(0.109 秒)
Speeding up lattice sieve with Xeon Phi coprocessor
Xeon Phi vector norm
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2017/6/22
Major substep in a lattice sieve algorithm which solves the Euclidean shortest vector problem (SVP) is the computation of sums and Euclidean norms of many vector pairs. Finding a solution to the SVP i...
Simple AEAD Hardware Interface (S艸I) in a SoC: Implementing an On-Chip Keyak/WhirlBob Coprocessor
Cryptographic coprocessor System-on-Chip Keccak
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2016/1/8
Simple AEAD Hardware Interface (S艸I) is a hardware cryptographic interface aimed at CAESAR Authenticated Encryption with Associated Data (AEAD) algorithms. Cryptographic acceleration is typically achi...
Lightweight Coprocessor for Koblitz Curves: 283-bit ECC Including Scalar Conversion with only 4300 Gates
elliptic curve cryptosystem implementation public-key cryptography
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2015/12/29
We propose a lightweight coprocessor for 16-bit microcontrollers
that implements high security elliptic curve cryptography. It uses
a 283-bit Koblitz curve and offers 140-bit security. Koblitz curve...
A coprocessor for secure and high speed modular arithmetic
countermeasure fault analysis side channel analysis high speed RNS FPGA
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2011/7/25
We present a coprocessor design for fast arithmetic over large numbers of cryptographic sizes. Our design provides a efficient way to prevent side channel analysis as well as fault analysis targeting ...
A coprocessor for secure and high speed modular arithmetic
implementation / FPGA side channel analysis fault analysis countermeasure RNS
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2012/3/27
We present a coprocessor design for fast arithmetic over large numbers of cryptographic sizes. Our design provides a efficient way to prevent side channel analysis as well as fault analysis targeting ...
A High Speed Pairing Coprocessor Using RNS and Lazy Reduction
implementation / RNS Moduli Selection Hardware Implementation of Pairing FPGA
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2012/3/28
In this paper, we present a high speed pairing coprocessor using Residue Number System (RNS) and lazy reduction. We show that combining RNS, which are naturally suitable for parallel architectures, an...
A High Speed Pairing Coprocessor Using RNS and Lazy Reduction
implementation RNS Moduli Selection Hardware Implementation of Pairing FPGA
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2011/6/9
In this paper, we present a high speed pairing coprocessor using Residue Number System (RNS) and lazy reduction. We show that combining RNS, which are naturally suitable for parallel architectures, an...
Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems
hyperelliptic curve hardware architecture coprocessor
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2009/3/20
Hardware accelerators are often used in cryptographic applications for speeding up the highly arithmetic-intensive publickey
primitives, e.g. in high-end smart cards. One of these emerging and very p...
A Coprocessor for the Final Exponentiation of the $\eta_T$ Pairing in Characteristic Three
characteristic three final exponentiation hardware accelerator FPGA
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2008/9/16
Since the introduction of pairings over (hyper)elliptic curves
in constructive cryptographic applications, an ever increasing number
of protocols based on pairings have appeared in the literature....