搜索结果: 1-15 共查到“routing”相关记录144条 . 查询时间(0.062 秒)
Academy of Mathematics and Systems Science, CAS Colloquia & Seminars：Capsule Aggregated Attention for Vehicle Routing Problems
车辆 路径问题 胶囊聚合 关注
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2023/4/27
Deep learning based methods have shown great potential for solving Vehicle Routing Problems (VRPs) in recent years. In the current learning based models, attention mechanism plays an important role an...
西安电子科技大学计算机通信与网络课件 Routing算法和路由协议
西安电子科技大学 计算机通信 网络 课件 算法 路由协议
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2019/4/30
西安电子科技大学计算机通信与网络课件 Routing算法和路由协议。
IMPROVED PUBLIC TRANSIT ROUTING ALGORITHM FOR FINDING THE SHORTEST K-PATH
Public transit routing Timetable Transfer penalty Multiple paths imilar paths
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2018/11/9
Most of the existing public transit routing algorithms were developed on the basis of graph theory. Recently, algorithms are being developed that can compute for O-D public transit paths by using time...
Privacy-Preserving Interdomain Routing at Internet Scale
BGP secure multi-party computation
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2017/5/11
The Border Gateway Protocol (BGP) computes routes between the organizational networks that make up today's Internet. Unfortunately, BGP suffers from deficiencies, including slow convergence, security ...
Predict the Multi-hop Reliability for Receiver Contention Based Routing in Dynamic Link Networks
Dynamic Link Networks Markov Chain Re- ceiver Contention Routing
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2016/1/23
We consider dynamic link networks(DLN), where nodes are static, but the links are highly dynamic. Reliable multi-hop communication is critical in such networks, which inspires receiver contention rout...
Mechanism Design for Resource Allocation with Applications to Centralized Multi-Commodity Routing
mechanism design strategyproof resource allocation net- work routing
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2016/1/22
We formulate and study the algorithmic mechanism design problem for a general class of resource allocation settings,where the center redistributes the private resources brought by individuals. Money t...
Early Propagation and Imbalanced Routing, How to Diminish in FPGAs
dual-rail precharge logic WDDL FPGA
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2016/1/9
This work deals with DPA-resistant logic styles, i.e., celllevel
countermeasures against power analysis attacks that are known as
a serious threat to cryptographic devices. Early propagation and imb...
Post-Quantum Forward-Secure Onion Routing (Future Anonymity in Today’s Budget)
Tor Onion routing Forward anonymity
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2016/1/5
The onion routing (OR) network Tor provides anonymity to its users by routing their encrypted
traffic through three proxies (or nodes). The key cryptographic challenge, here, is to establish symmetri...
New Internet Routing Method Allows Users to Avoid Sending Data Through Undesired Geographic Regions
New Internet Routing Method Users to Avoid Sending Data Undesired Geographic Regions
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2015/9/9
Censorship is one of the greatest threats to open communication on the Internet. Information may be censored by a user’s country of residence or the information’s desired destination. But recent studi...
TORCH:A Design Tool for Routing Channel Segmentation in FPGAs
FPGA segmentation routing architecture design
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2015/8/17
TORCH:A Design Tool for Routing Channel Segmentation in FPGAs.
Placement and Routing For A Field Programmable Multi-Chip Module
Placement Routing Field Programmable Multi-Chip Module
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2015/8/14
Placement and Routing For A Field Programmable Multi-Chip Module.
Segmented Channel Routing
Segmented Channel Routing
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2015/8/14
Segmented Channel Routing.
An FPGA Family Optimized for High Densities and Reduced Routing Delay
FPGA Family Optimized High Densities Reduced Routing Delay
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2015/8/14
An FPGA Family Optimized for High Densities and Reduced Routing Delay.
Chip-Firing and Rotor-Routing on Directed Graphs
Chip-Firing Rotor-Routing Directed Graphs
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2015/8/14
We give a rigorous and self-contained survey of the abelian sandpile model and rotor-router model on finite directed graphs, highlighting the connections between them. We present several intriguing op...
A New Statistical Model for Gate Array Routing
New Statistical Model Gate Array Routing
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2015/8/14
A new statistical model for routing of gate arrays is described. The model takes into consideration the effect of gate utilization on wiring area requirement. Model computed wiring area estimates sugg...