搜索结果: 1-15 共查到“军事学 processor”相关记录17条 . 查询时间(0.046 秒)
Accelerated V2X provisioning with Extensible Processor Platform
V2X SCMS Curve25519
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2019/9/19
With the burgeoning Vehicle-to-Everything (V2X) communication, security and privacy concerns are paramount. Such concerns are usually mitigated by combining cryptographic mechanisms with suitable key ...
Vulnerability Analysis of a Soft Core Processor through Fine-grain Power Profiling
Cryptography FPGA microprocessor
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2019/6/26
Embedded microprocessors are an important component of reconfigurable architectures. Fine-grain (e.g., cycle-accurate) power analysis of such processors has been used to improve power and energy effic...
An FPGA-based programmable processor for bilinear pairings
public-key cryptography implementation applications
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2018/11/2
Bilinear pairings on elliptic curves are an active research field in cryptography. First cryptographic protocols based on bilinear pairings were proposed by the year 2000 and they are promising soluti...
Secure Boot and Remote Attestation in the Sanctum Processor
secure boot remote attestation Physical Unclonable Function
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2018/5/11
During the secure boot process for a trusted execution environment, the processor must provide a chain of certificates to the remote client demonstrating that their secure container was established as...
Practical Evaluation of Masking Software Countermeasures on an IoT processor
IoT masking side channel attacks
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2017/5/11
Implementing cryptography on Internet-of-Things (IoT) devices, that is resilient against side channel analysis, has so far been a task only suitable for specialist software designers in interaction wi...
Biometric Based Network Security Using MIPS Cryptography Processor
Biometric Network Security Cryptograph
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2016/12/10
The empowerment in network on chip (NOC) and System on chip (SOC) in Microelectronics and Sensors have developed the various wireless communication Network technologies. In the past few years, many re...
Fast Modular Arithmetic on the Kalray MPPA-256 Processor for an Energy-Efficient Implementation of ECM
Kalray MPPA-256 manycore processor Multiprecision modular arithmetic Integer factorization
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2016/4/13
The Kalray MPPA-256 processor is based on a recent low-energy manycore architecture. In this article, we investigate its performance in multiprecision arithmetic for number-theoretic applications. We ...
Cross Processor Cache Attacks
Invalidate+Transfer Cross-CPU attack HyperTransport
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2015/12/21
Multi-processor systems are becoming the de-facto standard
across different computing domains, ranging from high-end
multi-tenant cloud servers to low-power mobile platforms.
The denser integration...
An Application Specific Instruction Set Processor (ASIP) for the Niederreiter Cryptosystem
Cryptographic hardware and implementation Application Specific Instruction Set Processor Niederreiter cryptosystem
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2015/12/18
The Niederreiter public-key cryptosystem is based
on the security assumption that decoding generic linear binary
codes is NP complete, and therefore, is regarded as an alternative
post-quantum solu...
A Fast Implementation of the Optimal Ate Pairing over BN curve on Intel Haswell Processor
optimal ate pairing efficient implementation
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2014/3/12
We present an efficient implementation of the Optimal Ate Pairing on Barreto-Naehrig curve over a 254-bit prime field on Intel Haswell processor. Our library is able to compute the optimal ate pairing...
Efficient Implementation of Grand Cru with TI C6x+ Processor
Grand Cru Keyed Structure of AES-128 DSP Implementation of Grand Cru
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2011/7/25
Grand Cru, a candidate cipher algorithm of NESSIE project, is based on the strategy of multiple layered security and derived from AES-128.
Efficient Implementation of Grand Cru with TI C6x+ Processor
implementation / Grand Cru Keyed Structure of AES-128 DSP Implementation of
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2012/3/27
Grand Cru, a candidate cipher algorithm of NESSIE project, is based on the strategy of multiple layered security and derived from AES-128. This algorithm was not selected for second phase evaluation o...
An Evaluation of Hash Functions on a Power Analysis Resistant Processor Architecture
message authentication codes hash functions smart cards
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2010/12/6
Cryptographic hash functions are an omnipresent components in security-critical software and devices; they support, for example, digital signature and data authenticity schemes, mechanisms for key der...
A Fast Implementation of T Pairing in Characteristic Three on Intel Core 2 Duo Processor
T pairing parallel computing efficient implementation SSE
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2009/6/11
We present an efficient implementation of T pairing on Intel Core 2 Duo
processor. The processing speed of our implementation achieves 92 sec
over F97 3 and 553 sec over F193 3 on 2.6GHz processor...
A Dedicated Processor for the eta Pairing
Dedicated Processor eta Pairing
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2009/3/5
A Dedicated Processor for the eta Pairing.